The focus of this project is on the development of an Informed Caching Environment (ICE) that relies on the cooperation of hardware and software for memory hierarchy management. We believe that a small number of hardware mechanisms can be used by software to efficiently manage the memory hierarchy, and improve overall performance. These mechanisms will complement (rather than replace) existing caching techniques.
Alvin Lebeck
Srikanth Srinivasan
Chia-Lin Yang
Mithuna Thottethodi
Locality vs. Criticality, S. Srinivasan, R. Ju, A. R. Lebeck, C. Wilkerson, in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2001.
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications, Chia-Lin Yang, Barton Sano, and Alvin R. Lebeck, in IEEE Transactions on Computers, September 2000.
Push vs. Pull: Data Movement for Linked Data Structures, Chia-Lin Yang and Alvin R. Lebeck, International Conference on Supercomputing 2000 (ICS '00), May 2000.
Load Latency Tolerance In Dynamically Scheduled Processors, Srikanth T. Srinivasan and Alvin R. Lebeck, Journal of Instruction-Level Parallelism (JILP), Volume 1, October 1999 ( http://www.jilp.org/vol1) Invited Paper
Annotated Memory References: A Mechanism for Informed Cache Management , A. R. Lebeck, D. R. Raymond, C. Yang, M. S. Thottethodi, Euro-Par '99, August 1999. (Short Version)
Load Latency Tolerance In Dynamically Scheduled Processors, Srikanth T. Srinivasan and Alvin R. Lebeck. In ACM/IEEE International Symposium on Microarchitecture (MICRO), November 1998, Best Paper Award
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications, Chia-Lin Yang, Barton Sano, and Alvin R. Lebeck, ACM/IEEE International Symposium on Microarchitecture (MICRO), November 1998
Annotated Memory References: A Mechanism for Informed Cache Management, Alvin R. Lebeck, David R. Raymond, Mithuna S. Thottethodi, Technical Report CS-1998-02, Febrary 1998, Computer Science Department, Duke University.
Exploiting Load Latency Tolerance in Dynamically Scheduled Processors, Srikanth T. Srinivasan and Alvin R. Lebeck, Technical Report CS-1998-03, February 1998, Computer Science Department, Duke University.
Last updated Monday, April 09, 2001