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[Fwd: Code Compression]



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Date: Mon, 19 Oct 1998 13:58:04 -0500
From: Andy Glew <glew@cs.wisc.edu>
Organization: U Wisc CS (& Intel)
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Subject: Code Compression
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Just in case any of you felt that I was crazy espousing compression
in the memory hierarchy, IBM is doing it, albeit for code only.

Compression for data is the obvious next step. I can show you how.

*** IBM Introduces Code Compression for PowerPC

At last week's Embedded Processor Forum, IBM's chief architect for embedded
PowerPC,
Tom Sartorius, revealed that IBM has developed a code-compression system
for
embedded PowerPC chips that can shrink code size by as much as 40%. The
code-
compression system, called CodePack, is ready now. The first chip to use it
should
appear on the market in 2Q99.

IBM's CodePack is fundamentally different from ARM's Thumb or MIPS' MIPS-16
code-
compression techniques. Rather than supplement the PowerPC instruction set
with a
second, 16-bit format, CodePack actually compresses object code, like
running PKZip
on a finished program. IBM claims a better overall compression ratio than
its
competitors, and CodePack can be applied to any PowerPC program or PowerPC
chip,
past, present, or future. It also does not interfere with software tools
such as
assemblers, compilers, or linkers.

CodePack uses an adaptive compression algorithm to squeeze the most out of
each
program. After the compressed object code is stored in memory, special
CodePack
hardware on the microprocessor decompresses the code in real time as it is
fetched
from memory but before it is executed. Although there is a slight
performance
penalty for this decompression, the extra latency is felt only during
instruction-
cache misses. Overall, CodePack is an interesting and unique approach to an
old
problem of minimizing the memory usage of high-performance embedded RISC
processors.





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