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[Fwd: Alpha 21364 Info]



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Rick Kessler, a former colleague of mine at UW-Madison is one of the
lead architects on the 21364.

	-alvy
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From: Milo Martin <milo@cs.wisc.edu>
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Subject: Alpha 21364 Info
To: architecture@cs.wisc.edu
Date: Fri, 23 Oct 1998 22:18:02 -0500 (CDT)
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UW-Architects - 

FYI, there was a presentation on the Alpha 21364 by Peter Bannon at
the 1998 Microprocessor Forum.  The slides are available at:
  http://www.digital.com/alphaoem/present/index.htm

I have summarized the more interesting information from the slides
below:

- Starts with some IA-64 bashing and an update on the 21164PC 
  and 21264. [Slides 1-11]
- Each 21364 contains a single Alpha 21264 core (at 1000+ Mhz)
- 100 million transistors (8 million logic, 92 million RAM)
- L1 caches - 64kB, 2-way set-assoc. inst. & data (like 21264)
- L2 cache - fully integrated, 1.5MB, 6-way SA, 
  12ns (~12 cycle) hit latency
- Integrated memory controller (Direct RAMbus)
- Integrated network interface 
  - Directory based cache coherence (DSM/NUMA)
  - Point-to-point with asynchronous clocking between processors
  - Out-of-order network with adaptive routing
  - 15ns processor-to-processor latency
  - torus topology for the network - North, South, East, West links

It appears from the slides that you can wire the processors and some
RAMbus chips together into a mesh and have a distributed shared
memory/directory based MP with no additional support chips.

-- 
Milo M. Martin (milo@cs.wisc.edu)      Maintainer of the 
http://www.cs.wisc.edu/~milo           WWW Computer Architecture Home Page
Computer Science Graduate Student      http://www.cs.wisc.edu/arch/www/
University of Wisconsin - Madison







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