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Re: CNN - IBM chip breaks memory bottleneck
- From: "Alvin R. Lebeck" <alvy@cs.duke.edu>
- Newsgroups: duke.cs.os-research
- Subject: Re: CNN - IBM chip breaks memory bottleneck
- Date: Thu, 25 Feb 1999 10:25:10 -0500
- Organization: Duke University
- References: <7b18ul$d9$1@hal.cs.duke.edu>
- To: Mithuna Thottethodi <mithuna@cs.duke.edu>
- Xref: news.duke.edu duke.cs.os-research:255
I don't think you want the application/compiler explicitly moving data
in and out. You can maybe do something like virtual memory with it, but
then isn't it just a software controlled cache? Also, remember access
time to a memory structure is a function of its size, so you may still
want a smaller cache for faster access time, and the ability to provide
multiple ports for a superscalar processor.
-alvy
Mithuna Thottethodi wrote:
>
> 32MB SRAM on the same chip as a micro processor!! Do we need caches any
> more?
>
> <quote>
> The technology giant has created a microprocessor that
> combines computation abilities with a vastly increased
> high-speed memory -- up to 32 megabytes -- on a single
> chip. Most of today's processors must frequently exchange
> data with separate memory chips, creating a performance
> bottleneck. The application-specific integrated circuit, or
> ASIC, will use copper circuitry as small as 0.15 micron (less
> than 1/600th the width of a human hair), creating a faster
> chip.
> </quote>
>
> Full report is available at
> http://www.cnn.com/TECH/computing/9902/23/ibm.memory.lat/
--
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