We are approaching an era where Moore's Law is facing increasing challenges, due to anticipated physical limits of further miniaturization of micro-electronics and ever increasing costs of chip masks and next generation fabrication plants for conventional CMOS. This led the Semiconductor Industry Association to call for implementation of non-CMOS solutions.
A new bottom up process for nanoelectronic integration by using DNA self-assemblies to produce a patterned nano-structure scaffold (called DNA lattice), to which carbon nanotubes are attached, along with its impact on computer architecture, is being explored under the project titled Troika at Duke Computer Science Department.
One of the goals of Troika is to explore what changes will be required in automated circuit layout techniques. This second year project tries to answer this question. Layout problem for nano-scale circuits becomes different in nature from that of VLSI circuits, mainly due to shortage of interconnects, small sizes (in terms of transistors) of nano-scale circuits and changed design rules for a new technology. Aim of this 2nd year project is to develop automated layout tools for nano-scale circuits laid out on a DNA lattice of size at most 50X50. The generated layout should ensure full routability and try and minimize area occupied on DNA lattice. The second goal of the project is to do seamless interfacing with other nanoscale design tools to form a coherent Design Tool Suite. This requires interfacing with custom DNA assembler Tool and developing Circuit Extractor tool to back-annotate the original circuit with wire models and parasitics derived from geometry of layout and feed it back in SPICE for more accurate circuit behavior simulation.
Some progress has been made towards meeting these goals. We have an
automatic layout generator that generated acceptable layout for small
circuits such as NAND gate and full adder. Also interfacing with the DNA
assembler has been done. The circuit to be laid out can be specified in
block level netlist format where the block can be n-fet, p-fet or any
other logic gate. Future works need to be done in modifying the routing
algorithm to modify and rip-up existing connections, developing circuit
extractor and trying layout of larger circuits. If automated layout of
larger circuits seem unacceptable, then we will switch to manual layout
and a convenient front-end will be provided.