This is a general timetable for Compsci 220 / ECE 252, it is updated as I go and may change.
The HW #X indicates homework due dates.
To access the various papers you must be on a Duke IP address.

8/31 Unit 0: Intro/Overview (HP: Ch 1)
Slides: 2up, 6up
9/2 Unit 1:Technology, Cost, Perf, etc.
Slides: 2up, 6up
9/7 Unit 1: Continued
  • Power a First-Class Architectural Design Constraint
  • A Case for Energy-Proportional Computing
  • 9/9 Finish Tech, power, etc., start Pipelining: Hazards (HP: Appendix A)
    Slides: 2up, 6up
    9/14 Pipelining: Speculation (HP: Appendix A)
    HW #1
  • The Optimal Pipeline Depth Per Pipeline Stage is 6-8 FO4 Inverter Delays
  • 9/16 Branch Prediction / start superscalar (HP: Ch 2 & 3)
    9/21 Superscalar (HP: Ch 2 & 3)
    Slides: 2up, 6up
    9/23 Static ILP
  • EPIC: Explicitly Parallel Instruction Computing
  • 9/28 Predicated Execution & Dynamic ILP (Scoreboard)
    Slides: 2up, 6up
    HW #2
    9/30 Dynamic ILP (Tomasulo)
    Slides: 2up, 6up
    10/5 Dynamic ILP (P6 & R10K)
    Slides: 2up, 6up
  • Complexity-Effective Superscalar Processors
  • Continual Flow Pipeline Processors
  • 10/7 Dynamic ILP
    Slides: See previous
  • Forwardflow: a scalable core for power-constrained CMPs
  • Multiscalar Processors
  • 10/12 Fall Break 10/14 Discuss Papers
    Project Proposal
    HW #3 (Friday, 10/15)
    10/21 Cache Memory (HP: Ch 5)
    Slides: 2up, 6up
    10/26 Cache Memory
    Slides: 2up, 6up
    10/28 Cache Memory
    Slides: 2up, 6up
  • An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches
  • Selective Cache Ways: On-demand Resource Allocation
  • 11/2 Memory Systems
    Slides: 2up, 6up
    11/4 Finish Memory Systems; start Multithreading (HP: Ch 4)
    Slides: 2up, 6up
    11/9 Multiprocessors
    2up, 6up
    11/11 Multiprocessors
    HW #4 Due
    Project Status Due Sunday Nov 14,11:59pm
  • Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
  • Simultaneous Speculative Threading: A Novel Pipeline Architecture Implemented in Sun's ROCK Processor
  • 11/16 Finish Multiprocessors (Synchronization & Consistency)
    2up, 6up
    11/18 Data Parallel, Vectors & GPGPU
    2up, 6up
  • NVidia Tesla: A Unified Graphics and Computing Architecture
  • 11/23 Fault Tolerance
  • Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
  • DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
  • 11/25 Thanksgiving Break
    11/30 Storage (Ch 6)
    Slides: 2up, 6up
    Virtual Machines
  • Virtual Machine Monitors: Current Techology and Future Trends
  • RIFLE: An Architectural Framework for User-Centric Information-Flow Security
  • 12/2
    HW #5 Due Emerging Technologies
  • A Defect Tolerant Self-organizing Nanoscale SIMD Architecture
  • Architectural Implications of Nanoscale Integrated Sensing and Computing
  • 12/7
    Project Work Day
    Final Project Report Due Friday Dec 10, 11:59pm
    Project Work Day
    Exam Week (Final Sun December 19 2pm-5pm in D106 LSRC)