H/P Chapter 1;

• "Instruction Sets and Beyond: Computers, Complexity, and Controversy"

H/P Appendix A; (I removed the paper.)

Hardware/Dynamic Exploitation of Instruction Level Parallelism

Superscalar Execution (6up, 2up)
Dynamic Scheduling: Scoreboard and Tomasulo (4up)
Dynamic Scheduling: Speculation and Precise Interrupts (4up)

H/P 2 and 3 (3 is optional);

• "The Microarchitecture of the Pentium 4 Processor";
  
• "Complexity-Effective Superscalar Processors";
  
• "Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors"
  

H/P Chapter 2;

• "EPIC: Explicitly Parallel Instruction Computing"

Cache Memory Review (2up, 6up)

Cache Memory Optimizations (2up, 6up)

Cache Memory & Main Memory(4up )

VirtualMemory(4up )

H/P Chapter 5;

• "An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches";
  
• "A Fully-Associative Software-Managed Cache Design";
  
• "Continual Flow Pipeline Processors"

Multithreading and Multiprocessors (4up)

H/P Chapter 4 (and 3.5);

• "Power a First-Class Architectural Design Constraint"
• "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor";
  
• "Multiscalar Processors";
  
• "Niagara: A 32-Way Multithreaded SPARC Processor"

Advanced Topics: Fault Tolerance, Virtual Machines, Security, Tiled/Grid Processors, Nanocomputing

Lebeck's talk on nano architectures

• "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design";
• "Argus: Low-Cost, Comprehensive Error Detection in Simple Cores";
• "Virtual Machine Monitors: Current Techology and Future Trends";
• "RIFLE: An Architectural Framework for User-Centric Information-Flow Security";
• "A Design Space Evaluation of Grid Processor Architectures";
• "A Defect Tolerant Self-organizing Nanoscale SIMD Architecture"