Reading assignments and changes will be announced in class and will be reflected in the following table.
| Date | Topic | Reading |
|---|---|---|
| Aug 30 Sep 1 Sep 3 |
Introduction and Overview
Data representations | Chapter 1, Chapter 4.1-4.3,4.8 (pp 275-280) |
| Sep 6 Sep 8 Sep 10 |
Memory and Bitwise Operations
Instruction Set Architectures (ISA) Overview, GPR, Stack, Memory-Memory | Chapter 3
Appendix A |
| Sep 13 Sep 15 Sep 17 | MIPS 2000 ISA and MIPS Assembly programming
Assembly Language Programming; The SPIM simulator | Chapter 3
Appendix A |
| Sep 20 Sep 22 Sep 24 | Assembly Language Programming (Cont.)
Procedure Calls | Chapter 3
Appendix A |
| Sep 27 Sep 29 Oct 1 | Boolean Algebra, Logic Gates
Review Test #1 | Appendix B
Chapter 4 |
| Oct 4 Oct 6 Oct 8 | Basic Logic design
The ALU, Memory Elements, Busses, Registers | Appendix B
Chapter 4 |
| Oct 11 | FALL BREAK (10/9/99 - 10/12/99) | |
| Oct 13 Oct 15 | Memory Elements, Busses, Registers, Integer Arithmetic
Building a Datapath | Appendix B
Chapter 4 Chapter 5 |
| Oct 18 Oct 20 Oct 22 | A Single cycle data path
Control for a single cycle processor | Chapter 5.3
Chapter 5.4 |
| Oct 25 Oct 27 Oct 29 | Memory Systems
Cache Memory | Chapter 7 |
| Nov 1 Nov 3 Nov 5 | Cache Memory (Cont.)
Review Test #2 | Chapter 7 |
| Nov 8 Nov 10 Nov 12 | Virtual Memory | Chapter 7.4 |
| Nov 15 Nov 17 Nov 19 | Input/Output & Storage devices
Input/Output Buses | Chapter 8 |
| Nov 22 Nov 24 | Input/Output, Iterrupts & Exceptions
Catch Up | Chapter 8 |
| Nov 26 | THANKSGIVING BREAK (11/25/99=PM - 11/28/98) | |
| Nov 29 Dec 1 Dec 3 | Pipelined Processor.
Superscalar Procesors; Multiprocessors | Chapter 6
Chapter 9 |
| Dec 6 Dec 8 |
Catch Up
Review | |
| Dec 17 | Final Exam, Friday, 9:00am-12:00n, B101 LSRC | |