A Parallel Algorithm for Planar Orthogonal Grid Drawings

R. Tamassia, I. G. Tollis, and J. S. Vitter. ``A Parallel Algorithm for Planar Orthogonal Grid Drawings,'' Parallel Processing Letters, March 2000. An extended abstract appears in ``Lower Bounds and Parallel Algorithms for Planar Orthogonal Grid Drawings,'' Proceedings of the 3rd IEEE Symposium on Parallel and Distributed Processing (SPDP '91), Dallas, TX, December 1991, 386-393.

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In this paper we consider the problem of constructing planar orthogonal grid drawings (or more simply, layouts) of graphs, with the goal of minimizing the number of bends along the edges. We present optimal parallel algorithms that construct graph layouts with O(n) maximum edge length, O(n²)area, and at most 2n+4 bends (for biconnected graphs) and 2.4n + 2bends (for simply connected graphs). All three of these quality measures for the layouts are optimal in the worst case for biconnected graphs. The algorithm runs on a CREW PRAM in $O(\log n)$ time with $n/\log n$ processors, thus achieving optimal time and processor utilization. Applications include VLSI layout, graph drawing, and wireless communication.