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Efficient Sorting using Registers and Caches

R. Wickremesinghe, L. Arge, J. S. Chase, and J. S. Vitter, ``Efficient Sorting using Registers and Caches,'' submitted to special issue of ACM Journal of Experimental Algorithmics. A shortened earlier version appears in Proceedings of the 4rd Workshop on Algorithm Engineering (WAE '00), Saarbrücken, Germany, September 2000.

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Modern computer systems have increasingly complex memory systems. Common machine models for algorithm analysis do not reflect many of the features of these systems, e.g., large register sets, lockup-free caches, cache hierarchies, associativity, cache line fetching, and streaming behavior. Inadequate models lead to poor algorithmic choices and an incomplete understanding of algorithm behavior on real machines. A key step toward developing better models is to quantify the performance effects of features not reflected in the models. This paper explores the effect of memory system features on sorting performance. We introduce a new cache-conscious sorting algorithm, R-MERGE, which achieves better performance in practice over algorithms that are superior in the theoretical models. R-MERGE is designed to minimize memory stall cycles rather than cache misses by considering features common to many system designs.


next up previous
Next: Duality Between Prefetching and Up: COMBINATORIAL ALGORITHMS AND COMBINATORIAL Previous: Distribution Sort with Randomized
Jeff Vitter
2008-07-05