#header begin

#include <stdio.h>

extern int stepsize;

/*
 * $Header: /usr/helios1/csc/dmanew/netlist/hl/RCS/clock.hlc,v 1.1
 * 88/09/05 12:00:51 rdp Exp Locker: rdp $ 
 */
/*-
 *           ____        ____        ____        ____
 * Phi1H ____|  |________|  |________|  |________|  |_____
 *
 *                 ____        ____        ____        ____
 * Phi2H __________|  |________|  |________|  |________|  |_____
 *
 */

#define MAX_I_PORTS 29
#define MAX_O_PORTS 29
#define MAX_IO_PORTS 13
#define NextArg(option) \
    if (++i == targc) { \
	fprintf(stderr,"Please provide argument for -%c flag\n",option);\
	return (0); }
#define Verify(X,Y)  \
    if (X == NULL) { \
	fprintf(stderr, "Could not find %s %s\n", Y, targv[i]); return (0); }
#define Fatal(X,Y) {fprintf(stderr,X,Y);exit(1);}
#define Message(X,Y) {fprintf(stderr,X,Y);return(0);}


int Stable1(), Qual2Low(), Qual1(), Stable2(), Qual1Low(), Qual2();
int ALLDONE = 0, Cycle = 0, Output = 0;
int WalkM = 2, Report = 3;
bptr statenodes;
FILE *statefile = NULL;

struct tv_data {
    bptr Input[MAX_I_PORTS], Output[MAX_O_PORTS], IO[MAX_IO_PORTS];
    nptr Reset, Phi, Test, IO_Enable[MAX_IO_PORTS];
    int ii_indx, oo_indx, io_indx, enable;
    char test_name[50];
    FILE *fp;
}   TV;

/* Define printout characters */
char *ii[4] = {"0991", "2993", "4995", "6997"};
char *io[4] = {"Z99Y", "2993", "4995", "6997"};
char *oo[4] = {"LXXH", "IXXJ", "MXXN", "PXXQ"};

init_tv()
{
    int i, j;

 /* Initialize */
    TV.enable = 1;
    if (strlen(TV.test_name) == 0)
	strcpy(TV.test_name,"testname_goes_here");

 /* Print vector header */
    fprintf(TV.fp, "vectors \n{\nvector_order = ( ");
    if (TV.Phi != NULL)
	fprintf(TV.fp, "%s", TV.Phi->nname);
    if (TV.Reset != NULL)
	fprintf(TV.fp, ", %s", TV.Reset->nname);
    if (TV.Test != NULL)
	fprintf(TV.fp, ", %s", TV.Test->nname);
    for (i = 0; i < TV.ii_indx; i++)
	for (j = 0; j < TV.Input[i]->nbits; j++)
	    fprintf(TV.fp, ", %s", TV.Input[i]->nodes[j]->nname);
    for (i = 0; i < TV.oo_indx; i++)
	for (j = 0; j < TV.Output[i]->nbits; j++)
	    fprintf(TV.fp, ", %s", TV.Output[i]->nodes[j]->nname);
    for (i = 0; i < TV.io_indx; i++)
	for (j = 0; j < TV.IO[i]->nbits; j++)
	    fprintf(TV.fp, ", %s", TV.IO[i]->nodes[j]->nname);
    fprintf(TV.fp, " );\ndata: %s\n{\n", TV.test_name);
}

output_state(outfile, nodes)
FILE *outfile;
bptr nodes;
{
    int i, j, flag;
    static int count;


    if (outfile != NULL) {
	for (i = 0; i < nodes->nbits; i++)
	    fprintf(outfile, "%c", "LXXH"[nodes->nodes[i]->npot]);
	fprintf(outfile, "; %d\n", count++);
	fflush(outfile);
    }
    if (TV.enable) {
	flag = (TV.Reset == NULL) ? 0 : (TV.Reset->npot == HIGH);

	if (TV.Phi != NULL){
	    if (TV.Phi->npot == HIGH)
		return;
	    fprintf(TV.fp, "%c", ii[0][TV.Phi->npot]);
	}
	if (TV.Reset != NULL)
	    fprintf(TV.fp, "%c", ii[0][TV.Reset->npot]);
	if (TV.Test != NULL)
	    fprintf(TV.fp, "%c", ii[0][TV.Test->npot]);
	fprintf(TV.fp, " ");

	for (i = 0; i < TV.ii_indx; i++){
	    for (j = 0; j < TV.Input[i]->nbits; j++)
		fprintf(TV.fp, "%c", ii[0][TV.Input[i]->nodes[j]->npot]);
	    fprintf(TV.fp, " ");
	}

	for (i = 0; i < TV.oo_indx; i++){
	    for (j = 0; j < TV.Output[i]->nbits; j++)
		fprintf(TV.fp, "%c",
		    flag ? 'X' : oo[0][TV.Output[i]->nodes[j]->npot]);
	    fprintf(TV.fp, " ");
	}

	for (i = 0; i < TV.io_indx; i++) {
	    if (TV.IO_Enable[i]->npot == HIGH) {
		for (j = 0; j < TV.IO[i]->nbits; j++)
		    fprintf(TV.fp, "%c",
			flag ? 'X' : oo[0][TV.IO[i]->nodes[j]->npot]);
	    }
	    else if (TV.IO_Enable[i]->npot == LOW) {
		for (j = 0; j < TV.IO[i]->nbits; j++)
		    fprintf(TV.fp, "%c", io[0][TV.IO[i]->nodes[j]->npot]);
	    }
	    else
		for (j = 0; j < TV.IO[i]->nbits; j++)
		    fprintf(TV.fp, "?");
	    fprintf(TV.fp, " ");
	}
	fprintf(TV.fp, "; %d\n", Cycle);
	fflush(TV.fp);
    }
}
#header end

#control k 
int maxcycles, endcycles;

static nptr TestHS1, Phi, Phi1H, Phi2H, TestHHQ1, Phi1L, Phi2L, TestLHQ1;
static int TPhi12b, TPhi1, NonPhi12, TPhi12a, TPhi;

int i, j;

if ((Phi2H == NULL) && (Phi == NULL)) {
    Phi = find("Phi");
    Phi1H = find("Phi1H");
    Phi2H = find("Phi2H");
    Phi1L = find("Phi1L");
    Phi2L = find("Phi2L");
    TestHS1 = find("TestHS1");
    TestHHQ1 = find("TestHHQ1");
    TestLHQ1 = find("TestLHQ1");
    TPhi12a = stepsize * 7 / 10;
    NonPhi12 = stepsize / 5;
    TPhi = TPhi12a + NonPhi12;;
    TPhi12b = stepsize - TPhi;
    TPhi1 = stepsize - NonPhi12;
}
maxcycles = (targc > 1) ? atoi(targv[1]) : 1;
endcycles = (targc > 2) ? atoi(targv[2]) : 0;

if (Phi == NULL)
{			    /* NO CLOCK GENERATOR  */
 /* insure that Phi1 is low */
if (Phi1H != NULL)
    setin(Phi1H, 'l');
if (TestHHQ1 != NULL)
    setin(TestHHQ1, 'l');
if (TestLHQ1 != NULL)
    setin(TestLHQ1, 'l');

 /* always start at end of Phi2 */
setin(Phi2H, 'h');
if (Phi2L != NULL)
    setin(Phi2L, 'l');
if (Phi1L != NULL)
    setin(Phi1L, 'h');

for (i = 0, j = 0; (i < maxcycles) && (j <= endcycles); i++) {
 /* End of Phi2 Phase */
    if (WalkM > 0)
	walk_module(Stable1);
    cdostep(TPhi12b);

 /* Non-Overlap phase */
    if (WalkM > 1)
	walk_module(Qual2Low);
    setin(Phi2H, 'l');
    if (Phi2L != NULL)
	setin(Phi2L, 'h');
    cdostep(NonPhi12);

 /* Phi1 Phase */
    if (WalkM > 1)
	walk_module(Qual1);
    if (Phi1H != NULL)
	setin(Phi1H, 'h');
    if (Phi1L != NULL)
	setin(Phi1L, 'l');
    if (TestHS1 != NULL) {
	if (TestHS1->npot == HIGH) {
	    if (TestHHQ1 != NULL)
		setin(TestHHQ1, 'h');
	}
	else if (TestLHQ1 != NULL)
	    setin(TestLHQ1, 'h');

    }
    else if (TestLHQ1 != NULL)
	setin(TestLHQ1, 'h');
    cdostep(TPhi12a);
    output_state(statefile, statenodes);
    if (Report == 3)
	wr_report();
    if (WalkM > 0)
	walk_module(Stable2);
    cdostep(TPhi12b);

 /* Non-Overlap Phase */
    if (WalkM > 1)
	walk_module(Qual1Low);
    if (Phi1H != NULL)
	setin(Phi1H, 'l');
    if (Phi1L != NULL)
	setin(Phi1L, 'h');
    if (TestHHQ1 != NULL)
	setin(TestHHQ1, 'l');
    if (TestLHQ1 != NULL)
	setin(TestLHQ1, 'l');
    cdostep(NonPhi12);

 /* Begin of Phi2 Phase */
    if (WalkM > 1)
	walk_module(Qual2);
    setin(Phi2H, 'h');
    if (Phi2L != NULL)
	setin(Phi2L, 'l');
    cdostep(TPhi12a);
    output_state(statefile, statenodes);
    if (Report && 1)
	wr_report();
    if(Output){
	lprintf(stdout, "\n ---------------------------- \n");
        lprintf(stdout, "           CYCLE %d", Cycle++);
        lprintf(stdout, "\n ---------------------------- \n");   
   }
 if (ALLDONE < 0)
	j++;
}
}
else {			    /* CLOCK GENERATOR CIRCUIT */

 /* insure that Phi1 is low - always start at end of Phi2 */
    setin(Phi, 'h');

    for (i = 0, j = 0; (i < maxcycles) && (j <= endcycles); i++) {
    /* End of Phi2 Phase */
	if (WalkM > 0)
	    walk_module(Stable1);
	cdostep(TPhi12b);

    /* Non-Overlap phase */
	if (WalkM > 1)
	    walk_module(Qual2Low);
	setin(Phi, 'l');
	cdostep(NonPhi12);
    /* Phi1 Phase */
	if (WalkM > 1)
	    walk_module(Qual1);
	cdostep(TPhi1);
	output_state(statefile, statenodes);
	if (Report == 3)
	    wr_report();
	if (WalkM > 0)
	    walk_module(Stable2);
	if (WalkM > 1)
	    walk_module(Qual1Low);
    /* Begin of Phi2 Phase */
	setin(Phi, 'h');
	cdostep(TPhi12b);
	if (WalkM > 1)
	    walk_module(Qual2);
	cdostep(TPhi1);
	output_state(statefile, statenodes);
	if (Report && 1)
	    wr_report();
	 if(Output){
          	lprintf(stdout, "\n ---------------------------- \n");
	        lprintf(stdout, "           CYCLE %d", Cycle++);
	        lprintf(stdout, "\n ---------------------------- \n");   
	}
	if (ALLDONE < 0)
	    j++;
    }
}
if (Report == 2)
    wr_report();
#control end

#control setclock
static int enable = 1;
int i, ndata, temp;
char option;

if (!enable)
    Message("No setclock definitions allowed after -Z flag\n", "");

for (i = 1; i < targc; i++) {
    if ((targv[i][0] != '-') || (targv[i][2] != '\0'))
	fprintf(stderr, "Unknown flag %s ignored\n", targv[i]);
    else
	switch (option = targv[i][1]) {
	  case 'R':
	    NextArg(option);
	    ndata = sscanf(targv[i], "%d", &temp);
	    if (ndata != 1)
		Message("Illegal value for option R - Report unchanged\n","");
	    Report = temp;
	    break;
	  case 'W':
	    NextArg(option);
	    ndata = sscanf(targv[i], "%d", &temp);
	    if (ndata != 1)
		Message("Illegal value for option W - WalkM unchanged\n","");
	    WalkM = temp;
	    break;
	  case 'S':
	    NextArg(option);
	    statenodes = findvector(targv[i]);
	    Verify(statenodes, "vector");
	    NextArg(option);
	    statefile = fopen(targv[i], "w");
	    if (statefile == NULL)
		Fatal("Could not open %s for output\n", targv[i]);
	    break;
	  case 'I':
	    if (TV.ii_indx == MAX_I_PORTS)
		Fatal("Maximum input ports (%d) exceeded\n", MAX_I_PORTS);
	    NextArg(option);
	    TV.Input[TV.ii_indx] = findvector(targv[i]);
	    Verify(TV.Input[TV.ii_indx], "vector");
	    TV.ii_indx++;
	    break;
	  case 'O':
	    if (TV.oo_indx == MAX_O_PORTS)
		Fatal("Maximum output ports (%d) exceeded\n", MAX_O_PORTS);
	    NextArg(option);
	    TV.Output[TV.oo_indx] = findvector(targv[i]);
	    Verify(TV.Output[TV.oo_indx], "vector");
	    TV.oo_indx++;
	    break;
	  case 'T':
	    if (TV.io_indx == MAX_IO_PORTS)
		Fatal("Maximum IO ports (%d) exceeded\n", MAX_IO_PORTS);
	    NextArg(option);
	    TV.IO[TV.io_indx] = findvector(targv[i]);
	    Verify(TV.IO[TV.io_indx], "vector");
	    NextArg(option);
	    TV.IO_Enable[TV.io_indx] = find(targv[i]);
	    Verify(TV.IO_Enable[TV.io_indx], "node");
	    TV.io_indx++;
	    break;
	  case 'V':
	    NextArg(option);
	    TV.fp = fopen(targv[i], "w");
	    if (TV.fp == NULL)
		Fatal("Could not open %s for output\n", targv[i]);
	    break;
	  case 'N':
	    NextArg(option);
	    strcpy(TV.test_name, targv[i]);
	    break;
	  case 'P':
	    NextArg(option);
	    TV.Phi = find(targv[i]);
	    Verify(TV.Phi, "node");
	    break;
	  case 'H':
	    NextArg(option);
	    TV.Test = find(targv[i]);
	    Verify(TV.Test, "node");
	    break;
	  case 'C':
	    NextArg(option);
	    TV.Reset = find(targv[i]);
	    Verify(TV.Reset, "node");
	    break;
	  case 'Z':
	    if (++i != targc)
		Message("-Z option must be the last argument\n", "");
	    if (TV.fp == NULL)
		Message("-V option must be executed before -Z\n", "");
	    if (TV.Reset == NULL)
		Message("-C option must be executed before -Z\n", "");
	    if (TV.Phi == NULL)
		Message("-P option must be executed before -Z\n", "");
	    enable = 0;
	    init_tv();
	    break;
	  default:
	    fprintf(stderr, "setclock: Unknown flag %s ignored\n", targv[i]);
	    break;
	}
}
#control end

#control iset
bptr v;
if (targc == 3) {
    if ((v = findvector(targv[1])) == NULL) {
	error("no such vector as  %s", targv[1]);
	return (0);
    }
    csetvector(v, atoi(targv[2]));
}
else {
    error("usage: iset vectorname value \n");
    return (0);
}

#control end

#module dummy()
#operator Stable1()
#operator end
#operator Stable2()
#operator end
#operator Qual1()
#operator end
#operator Qual2()
#operator end
#operator Qual1Low()
#operator end
#operator Qual2Low()
#operator end
#module end