CPS 104	 Problem PD

MYMIPS Hardware Modification

The following questions all refer to Lecture 12:  A MYMIPS CPU Data Path.

1.  Slide 19 presents a circuit diagram for one bit of one register (a
register "cell") of the MYMIPS register file.  Looking at that diagram, the
tri-state driver which drives Bus-B is drawn slightly differently than the
others.  Why?  What is the exact difference, what does the different circuit
do that is different from the other tri-state drivers shown?  Is the
circuit as drawn correct?

2.  Slide 5 gives a table of instructions, and encodings for the Branch
Conditional instruction's D-field.  Using the circuit on slide 8 as a basis,
draw the circuit that implements the Branch Conditional.  Explain how your
circuit is connected to the circuits shown in slide 8.  You may assume that
a signal "BRCND" is generated elsewhere which is true when the instruction
is in fact a Branch Conditional, and is false otherwise.  However, you
should draw the circuit which detects the ==0 and <0 conditions, and explain
exactly how these circuits are connected to the circuits on slide 8.
The circuit for the Branch Conditional should use the ==0 and <0, along with
other information, to determine whether to "branch" or not, and generate a
signal which can be connected into the circuit on slide 8 to accomplish
this.  Show also the circuits for the >0 condition.

3.  Bus C on slide 8 may or may not be "controllable" correctly.  Bus C may
be driven from: RFB, R.C (this stands for "Bus-C connection to the register
file, R"), and DM (Data memory).  However, it must not be driven EVER by two
different "sources" at the same time.  Develop a table which shows, for each
instruction, and each driver of Bus C, when that driver is activated.  The
names of the drivers are:
RFB.E, R.C.RE (Read Enable for R.C), DM.RE (Read out of Data Memory Enable).
Each driver is activated when set T, deactivated when set F, and you can
use X to indicate "don't care which value".  You may also indicate whether
the enable signal for a driver should be ANDed with CLK, or with NCLK,
outside the table.  Describe how you expect the circuit developed from the
table to implement the Bus C part of each of the instructions in the table
on slide 5.