Hardware Acceleration in the World of Emerging Applications
Semiconductor technology scaling coming to a screeching halt coupled with the explosion of data in almost every facet of our lives makes processing large volumes of data efficiently a critical problem to solve. In this talk, I will highlight three main challenges in designing accelerators and demonstrate that domain-specific hardware acceleration and specialization can provide orders of magnitude in compute efficiency for emerging applications. I will introduce the concept of datatype acceleration, where hardware primitives are designed to directly operate on already-defined software data structures and data containers, and show that specializing both the compute and memory subsystem provides orders of magnitude improvements in performance and energy efficiencies. Creating specialized encapsulated data accesses and datapaths allows us to mitigate unnecessary data movement, take advantage of traditional optimization techniques such as data and pipeline parallelism, and consequently provide substantial energy savings while obtaining significant performance gains. As case studies for three emerging application domains, I will briefly touch on accelerating database and graph analytics while offering in-depth examples in accelerating genomic analytics on the AWS EC2 F1 instances. As a vision for future hardware acceleration research, I will demonstrate how to create an ecosystem that makes designing, deploying, and using custom hardware almost as easy as writing and using software.
Lisa Wu is a postdoctoral researcher at the University of California, Berkeley. Prior to joining UC Berkeley, she was a research scientist at Intel Labs. Her research interests include computer architecture and microarchitecture, accelerators, hardware-software co-design, energy-efficient computing, and emerging applications related to big data such as database and graph analytics, and healthcare such as genomics analytics for precision medicine. Lisa has a PhD in computer science from Columbia University, a MS in computer science and engineering from the University of Michigan, Ann Arbor, and a BS in electrical and computer engineering from the University of Illinois, Urbana-Champaign. Prior to pursuing her doctorate, she was a computer and performance architect at Intel for many years, architecting various Xeon and IPF server processors including leading the Xeon Phi Vector Processing Unit architecture. Her work has received two IEEE Micro Top Picks selections and a MICRO best paper award.